`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10:45:57 10/07/05 // Design Name: // Module Name: LI-DAC // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module LIDAC(C0, C1, C2, C3, D, DB, S7, LDAC, A0, WR, STR, R, G, B, INT, UD1); input C0; input C1; input C2; input C3; input [7:0] D; output [11:0] DB; output S7; output LDAC; output A0; output WR; output STR; output R; output G; output B; output INT; output UD1; reg [11:0] DB; reg LDAC; reg A0; reg WR; reg STR; reg R; reg G; reg B; reg INT; reg UD1; reg C0h; reg C1h; reg C2h; wire clks; wire del1; wire del2; wire del3; wire del4; wire del5; wire del6; wire d_clocks; wire datclk; BUF tbbuf (tback,C3); BUF delay1 (del1,clks); BUF delay2 (del2,del1); BUF delay3 (del3,del2); BUF delay4 (del4,del3); BUF delay5 (del5,del4); BUF delay6 (del6,del5); assign d_clocks=del6; assign clks = (C0 && C1 && C2); // synthesis attribute noreduce of tback is yes; // synthesis attribute noreduce of del1 is yes; // synthesis attribute noreduce of del2 is yes; // synthesis attribute noreduce of del3 is yes; // synthesis attribute noreduce of del4 is yes; // synthesis attribute noreduce of del5 is yes; // synthesis attribute noreduce of del6 is yes; assign datclk = d_clocks ~^ clks; reg [2:0] state; parameter s0 = 3'b000; parameter s1 = 3'b001; parameter s2 = 3'b010; parameter s3 = 3'b011; parameter s4 = 3'b100; parameter s5 = 3'b101; parameter s6 = 3'b110; parameter s7 = 3'b111; always @(posedge datclk) case (state) s0: if (!C0) state<=s1; s1: begin A0=1'b0; WR=1'b0; DB[11:0]={D[7:0],4'b0000}; C0h<=1'b1; if (C0) state<=s2; end s2: begin WR=1'b1; C0h<=1'b0; if (!C1) state<=s3; end s3: begin A0=1'b1; WR=1'b0; DB[11:0]={D[7:0],4'b0000}; C1h<=1'b1; if (C1) state<=s4; end s4: begin WR=1'b1; C1h<=1'b0; if (!C2) state<=s5; end s5: begin LDAC=1'b0; //synchronous load of x & y dacs + RGB, blank, intensity & UD1 R=D[7]; //R 7 G=D[6]; //G 6 B=D[5]; //B 5 INT=D[0]; //blanking 0 STR=D[1]; UD1=D[2]; C2h<=1'b1; if (C2) state<=s6; end s6: begin LDAC=1'b1; C2h<=1'b0; if (!C0) state<=s1; end s7: if (!C0) state<=s1; endcase endmodule