`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    10:45:57 10/07/05
// Design Name:    
// Module Name:    popelDAC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module popeldac(C0, C1, C2, C3, D, DB, S7, LDAC, A0, WR, STR, R, G, 
                 B, INT, UD1);
    input C0;
    input C1;
    input C2;
    input C3;
    input [7:0] D;
    output [11:0] DB;
    output S7;
    output LDAC;
    output A0;
    output WR;
    output STR;
    output R;
    output G;
    output B;
    output INT;
    output UD1;

wire [11:0] DB;
wire LDAC;
reg A0;
reg WR;
wire STR;
wire R;
wire G;
wire B;
wire INT;
wire UD1;

reg C0h;
reg C1h;
reg C2h;
wire clks;
wire del1;
wire del2;
wire del3;
wire del4;
wire del5;
wire del6;
wire d_clocks;
wire datclk;


assign STR=1'b0;
assign S7=1'b0;
assign UD1=1'b0;
assign R=1'b0;
assign G=1'b0;
assign B=1'b0;
assign LDAC=1'b0;

BUF tbbuf (tback,C3);
BUF delay1 (del1,clks);
BUF delay2 (del2,del1);
BUF delay3 (del3,del2);
BUF delay4 (del4,del3);
BUF delay5 (del5,del4);
BUF delay6 (del6,del5);
assign d_clocks=del6;

assign INT=C0;

assign clks = (C1 && C2);
assign DB[11:0]={D[7:0],4'b0000};

// synthesis attribute noreduce of tback is yes;
// synthesis attribute noreduce of del1 is yes;
// synthesis attribute noreduce of del2 is yes;
// synthesis attribute noreduce of del3 is yes;
// synthesis attribute noreduce of del4 is yes;
// synthesis attribute noreduce of del5 is yes;
// synthesis attribute noreduce of del6 is yes;

assign datclk = d_clocks ~^ clks;

reg [1:0] state;

parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;

always @(posedge datclk)
case (state)


 s0: begin
  WR=1'b1; //store X DAC
  if (!C1) state<=s1;
  end

 s1: begin
  A0=1'b1; //select Y DAC
  WR=1'b0;
  if (C1) state<=s2;
  end

 s2: begin
  WR=1'b1; //store Y
  if (!C2) state<=s3;
  end

 s3: begin
  A0=1'b0; //select X DAC
  WR=1'b0; 
  if (C2) state<=s0;
  end

endcase

endmodule