Interface examples:


Update 1-Nov-05 – Added V1.0 of Popelscan DAC emulator.



The parallel port interface is configured by programming the CPLD.

The CPLD is a Xilinx XC9536 – a fairly simple device but more than adequate for handling any parallel interface you can throw at it.


If you want to develop on your own – you can download WebPACK free from Xilinx.

Webpack includes Impact – a tool to program the CPLD using the inbuilt Xilinx parallel programmer.

For anyone who does not want to download the whole of Webpack you can use the Altera JAM player software.


The example below is verilog code for an 8bit interface.

Xdata is buffered on the falling edge of  /C0

Ydata is buffered on the falling edge of  /C1

Xdata, Ydata, RGB, blank & shutter are latched on the falling edge of C2 - All synchronous :-)

The entire write cycle is 6 parallel port writes – 3 to 378h and 3 to 37Ah.




For WebPackers you need 8bitDAC.jed

For Jammers you need 8bitDAC.stapl – use the command line JAM –cx -aRUN_XILINX_PROC 8bitDAC.stapl



Popelscan DAC

I don’t have a schematic for this DAC so the only info I have to work on is from ‘scoping the parallel port.

It seems that Xdata is valid during both edges of C2 and Ydata is valid during both edges of C1.

C0 is blanking.  RGB data does not seem to be present. Anyone know any different? - please mail me.


V1.0 Updates X at the rising edge of C2 and Y at the rising edge of C1. C0 is fed to Blanking Out.

As the popelscan software has a slight delay between updating X and Y there is a brief period where the coordinates are the old Y but new X.

This shows as a faint ghost point when viewing the output in X-Y mode on an oscilloscope.

This will not be visible when using scanners.  I will update the code to buffer X & Y in the DAC then update both synchronously in popeldac V1.1.


Verilog code popeldac.v

Jed file (for impact) popeldac.jed

Stapl file (for JAM player) popeldac.stapl


Keep watching this space for downloads for common DACs

For developers I will email out the complete Xilinx file set including the UCF (user constraint file)


Next to appear will be 12bitsX, 12bitsY, RGB, blank and shutter in only 5 writes, all to 378h.